Dr. Sujit Kumar Patel

Designation:

Assistant Professor

Specialization:

VLSI Signal Processing

Email:

sujit.patel@thapar.edu

Subjects

Electrical Circuit Analysis, Electronic Devices and Circuits, Analog Electronics, Semiconductor Devices, Digital Electronics, Signals and Systems, VLSI Circuits & Systems Design, Analog VLSI Design

Membership of Professional Institutions, Associations, Societies

• IEEE Member

Publications and other Research Outputs

SCI/SSCI

1. B. K. Mohanty, P. K. Meher and S. K. Patel, “LUT optimization for distributed arithmetic based block least mean square adaptive filter,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1926-1935, May 2016.
2. P. K. Meher, B. K. Mohanty, S. K. Patel, S. Ganguly and T. Srikanthan, “Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data”, IEEE Transaction on Circuits and Systems-I, Regular Papers, vol.62, no.12, pp.2836-2845, Dec. 2015.
3. B. K. Mohanty, S. K. Patel, “Efficient very large-scale integration architecture for variable length block least mean square adaptive filter,” IET Journal on Signal Processing, vol. 9, no. 8, pp. 605-610, Oct. 2015.
4. B. K. Mohanty, S. K. Patel, “Area-delay-power efficient carry select adder,” IEEE Transaction on Circuits and Systems-II, Express Brief, vol. 61, no. 6, pp. 418-422, June 2014.

Description of Research Interests

VLSI Systems Design for Signal Processing Algorithms, Arithmetic Circuits for Signal Processing.